1. Field of the Invention
The present invention relates to an apparatus and method for driving a plasma display panel, and more particularly, to an apparatus and method for driving a plasma display panel, wherein electromagnetic interference is minimized and stability is improved.
2. Background of the Related Art
A plasma display panel (hereinafter, referred to as a ‘PDP’) is adapted to display an image including characters or graphics by light-emitting phosphors with ultraviolet of 147 nm generated during the discharge of a gas such as He+Xe, Ne+Xe or He+Ne+Xe. This PDP can be easily made thin and large, and it can provide greatly increased image quality with the recent development of the relevant technology. Particularly, a three-electrode AC surface discharge type PDP has advantages of lower driving voltage and longer product lifespan as a voltage necessary for discharging is lowered by wall charges accumulated on a surface upon discharging and electrodes are protected from sputtering caused by discharging.
FIG.1 is a perspective view illustrating the structure of a discharge cell of a conventional three-electrode AC surface discharge type PDP.
Referring now to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrodes Y and a sustain electrode Z which are formed on the bottom surface of an upper substrate 10, and an address electrode X formed on a lower substrate 18. The scan electrodes Y includes a transparent electrode 12Y, and a metal bus electrode 13Y which has a line width smaller than that of the transparent electrode 12Y and is disposed at one side edge of the transparent electrode. Further, the sustain electrode Z includes a transparent electrode 12Z, and a metal bus electrode l3Z which has a line width smaller than that of the transparent electrode l2Z and is disposed at one side edge of the transparent electrode.
The transparent electrodes 12Y and 12Z, which are generally made of ITO (indium tin oxide), are formed on the bottom surface of the upper substrate 10. The metal bus electrodes 13Y and 13Z are generally formed on the transparent electrodes 12Y and 12Z made of metal such as chromium (Cr), and serves to reduce a voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. On the bottom surface of the upper substrate 10 in which the scan electrodes Y and the sustain electrode Z are placed parallel to each other is laminated an upper dielectric layer 14 and a protective layer 16. The upper dielectric layer 14 is accumulated with a wall charge generated during plasma discharging. The protective layer 16 is adapted to prevent damages of the upper dielectric layer 14 due to sputtering caused during plasma discharging, and improve efficiency of secondary electron emission. As the protective layer 16, magnesium oxide (MgO) is generally used.
A lower dielectric layer 22 and barrier ribs 24 are formed on the lower substrate 18 in which the address electrode X is formed. A phosphor layer 26 is applied to the surfaces of both the lower dielectric layer 22 and the barrier ribs 24. The address electrode X is formed on the lower substrate 18 in the direction in which the scan electrodes Y and the sustain electrode Z intersect with each other. The barrier ribs 24 are in the form of stripe or lattice to prevent leakage of an ultraviolet and a visible light generated by discharging to an adjacent discharge cell. The phosphor layer 26 is excited with an ultraviolet generated during the plasma discharging to generate any one visible light of red, green and blue lights. An inert mixed gas is injected into the discharge spaces defined between the upper substrate 10 and the barrier ribs 24 and between the lower substrate 18 and the barrier ribs 24.
This PDP is driven with one frame being time-divided into a plurality of sub-fields having a different number of emission in order to implement the gray scale of an image. Each of the sub fields is divided into an initialization period for initializing the entire screen, an address period for selecting a scan line and selecting a cell from the selected scan line, and a sustain period for implementing gray scales according to the number of discharging.
In this time, the initialization period is divided into a set-up period where a ramp-up waveform is applied, and a set-down period where a ramp-down waveform is applied. If it is desired to display an image with 256 gray scales, a frame period (16.67 ms) corresponding to 1/60seconds is divided into eight sub-fields SF1 to SF8, as shown in FIG. 2. Each of the sub-fields SF1 to SF8 is subdivided into the initialization period, the address period and the sustain period, as described above. The initialization period and the address period of each of the sub-fields SF1 to SF8 are the same every sub-field, whereas the sustain period increases in the ratio of 2n (where, n=0,1,2,3,4,5,6,7) in each sub-field.
FIG. 3 is a block diagram of an apparatus for driving a PDP in the prior art.
Referring to FIG. 3, the conventional apparatus for driving the PDP includes an address driving unit 32 for driving address electrodes X1 to Xm disposed in a panel 30, a scan driving unit 34 for driving scan electrodes Y1 to Yn disposed in the panel 30, a sustain driving unit 36 for driving sustain electrodes Z1 to Zn disposed in the panel 30, a driving voltage generator 40 for supplying driving voltages to the driving units 32, 34 and 36, and a timing controller 38 for supplying control signals SCS1 to SCS3 to the driving units 32, 34 and 36.
The driving voltage generator 40 generates a variety of driving voltages so that a driving waveform as shown in FIG. 4 can be generated, and supplies the generated voltages to the address driving unit 32, the scan driving unit 34 and the sustain driving unit 36. For example, the driving voltage generator 40 generates voltages, such as Vsetup, −Vw, Vr and Vs, and supplies the voltages to the scan driving unit 34. It generates a voltage Vs, and provides the voltage to the sustain driving unit 36. Furthermore, the driving voltage generator 40 generates a voltage Va, and provides it to the address driving unit 32.
The timing controller 38 generates a variety of the switching control signals so that the driving waveform as shown in FIG. 4 can be generated, and supplies the generated switching control signals to the address driving unit 32, the scan driving unit 34 and the sustain driving unit 36. For example, the timing controller 38 generates a first switching control signal SCS1 and a second switching control signal SCS2, and supplies the signals to the scan driving unit 34 and the sustain driving unit 36, respectively. Also, the timing controller 38 generates a third switching control signal SCS3 and a data clock DCLK, and supplies them to the address driving unit 32.
The address driving unit 32 serves to supply image data, which are received from the outside, to the address electrodes X1 to Xm, under the control of the data clock DCLK and the third switching control signal SCS3, both of which are supplied from the timing controller 38.
The scan driving unit 34 supplies a reset pulse, a scan pulse scan and a sustain pulse sus to the scan electrodes Y1 to Ym, under the control of the first switching control signal SCS1 outputted from the timing controller 38.
The sustain driving unit 36 supplies a positive polarity voltage (Vs), the sustain pulse sus and an erase pulse erase to the sustain electrodes Z1 to Zn, under the control of the second switching control signal SCS2 outputted from the timing controller 38.
The driving waveform applied to the electrodes will now be described in detail with reference to FIG. 4. In a set-up period of the initialization period, a ramp-up waveform Ramp-up is applied to all the scan electrodes Y at the same time. A weak discharge is generated within cells of the entire screen by the ramp-up waveform Ramp-up, thus generating wall charges within the cells. In the set-down period, after the ramp-up waveform Ramp-up is applied, a ramp-down waveform Ramp-down, which falls from a voltage of the positive polarity that is lower than the peak voltage of the ramp-up waveform Ramp-up, is applied to the scan electrodes Y at the same time. The ramp-down waveform Ramp-down generates a weak erase discharge within the cells to erase the wall charges generated by a set-up discharge and unnecessary charges among space charges and also to allow the wall charges necessary for an address discharge to uniformly remain within the cells of the entire screen.
In the address period, simultaneous when the scan pulse scan of the negative polarity is sequentially applied to the scan electrodes Y, the data pulse data of the positive polarity is applied to the address electrodes X. As a voltage difference between the scan pulse scan and the data pulse data and the wall voltage generated in the initialization period are added, the address discharge is generated within cells to which the data pulse data is applied. The wall charges are generated within cells selected by the address discharge.
Meanwhile, during the set-down period and the address period, a positive DC voltage of the sustain voltage level (Vs) is applied to the sustain electrodes Z.
In the sustain period, the sustain pulse sus is alternately applied to the scan electrodes Y and the sustain electrodes Z. Then, in cells selected by the address discharge, a sustain discharge is generated in the form of a surface discharge between the scan electrodes Y and the sustain electrodes Z whenever every sustain pulse sus is applied as wall voltages within the cells and the sustain pulse sus are added. After the sustain discharge is completed, an erase ramp waveform erase having a small pulse width is applied to the sustain electrodes Z to erase the wall charges within the cells.
In such a conventional PDP, during the sustain period, the scan electrodes Y and the sustain electrodes Z are alternately applied with the sustain pulse sus. At this time, when the sustain pulse sus is supplied to the scan electrodes Y, the sustain electrodes Z is supplied with the ground voltage GND. When the sustain pulse sus is provided to the sustain electrodes Y, the scan electrodes Z is supplied with the ground voltage GND. That is, since a high current flows when the sustain pulse sus is provided to a given electrodes Y or Z, the remaining electrode to which the sustain pulse sus is not supplied is connected to the ground voltage GND, so that the operation is stabilized. However, during the sustain period, in order for the scan electrodes Y and the sustain electrodes Z to be connected to the sustain pulse sus and the ground voltage GND in an alternate way, switching means included in the scan driving unit 34 and the sustain driving unit 36 perform lots of switching operations. Accordingly, there is a problem in that high EMI is generated. Furthermore, in the prior art, since lots of switching means (i.e., line is long) are needed in order for the scan electrodes Y and the sustain electrodes Z to be connected to the ground voltage GND, there is a problem in that additional noise is generated.
Generally, in order to stabilize the operation of a PDP, any one of the scan electrodes Y and the sustain electrodes Z has to be connected to the ground voltage GND so that a voltage level can be stabilized. Practically, however, if any one of the scan electrodes Y and the sustain electrodes Z is connected to the ground voltage GND, introduction of external noise, generation of EMI, etc. can be minimized. In the prior art, however, since a variety of driving waveforms are supplied to the scan electrodes Y and the sustain electrodes Z, it is difficult to secure the stability of a PDP.
Moreover, in the prior art, the scan driving unit 34 and the sustain driving unit 36 include switching means which are connected to the scan electrodes Y and the sustain electrodes Z, respectively, in a push-pull type. If the switching means are connected in the push-pull type as such, lots of the switching means are needed. As a result, there are problems in that the manufacture cost is increased, leakage current is generated, etc.